18513649. INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Tzuan-Horng Liu of Taoyuan City (TW)
Chao-Hsiang Yang of Hsinchu City (TW)
Hsien-Wei Chen of Hsinchu City (TW)
Ming-Fa Chen of Taichung City (TW)
INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18513649 titled 'INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME
Simplified Explanation
The patent application describes an integrated circuit component with a semiconductor substrate, conductive pads, a passivation layer, and conductive vias.
- The semiconductor substrate has an active surface.
- The conductive pads are on the active surface, electrically connected to the substrate, and have contact and testing regions.
- The passivation layer covers the substrate, with the conductive pads between the substrate and the layer.
- The testing and contact regions of the pads are exposed by the passivation layer.
- The conductive vias are located on the contact regions of the pads.
Potential Applications
- Integrated circuits
- Semiconductor devices
- Electronics manufacturing
Problems Solved
- Ensuring proper electrical connections in integrated circuits
- Protecting semiconductor components from environmental factors
- Facilitating testing and troubleshooting of integrated circuits
Benefits
- Improved reliability of integrated circuits
- Enhanced performance of semiconductor devices
- Streamlined manufacturing processes
Original Abstract Submitted
An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
