18513544. ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH BACK END OF LINE (BEOL) CONNECTION IN A CARRIER WAFER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH BACK END OF LINE (BEOL) CONNECTION IN A CARRIER WAFER
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Wun-Jie Lin of Hsinchu City (TW)
Jam-Wem Lee of Hsinchu City (TW)
ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH BACK END OF LINE (BEOL) CONNECTION IN A CARRIER WAFER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18513544 titled 'ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH BACK END OF LINE (BEOL) CONNECTION IN A CARRIER WAFER
Simplified Explanation
The patent application discloses an electrostatic discharge (ESD) protection apparatus and method for fabricating the same.
- An internal circuit patterned in a device wafer and electrically coupled between a first node and a second node.
- An array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, electrically coupled between a first node and a second node, and configured to protect the internal circuit from transient ESD events.
- The device wafer is bonded to the carrier wafer.
Potential Applications
- Semiconductor manufacturing
- Electronics industry
- Integrated circuit design
Problems Solved
- Protection of internal circuits from transient ESD events
- Ensuring reliability of electronic devices
- Enhancing performance of electronic components
Benefits
- Improved ESD protection
- Enhanced reliability of electronic devices
- Increased lifespan of integrated circuits
Original Abstract Submitted
An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
