18513254. HIGH ESD IMMUNITY FIELD-EFFECT DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
HIGH ESD IMMUNITY FIELD-EFFECT DEVICE AND MANUFACTURING METHOD THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
HIGH ESD IMMUNITY FIELD-EFFECT DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18513254 titled 'HIGH ESD IMMUNITY FIELD-EFFECT DEVICE AND MANUFACTURING METHOD THEREOF
Simplified Explanation
The abstract describes an apparatus for providing electrostatic discharge (ESD) immunity, including a field effect transistor (FET), metal interconnect layer, power delivery network (PDN), and through substrate resistive component.
- The apparatus includes a FET formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process.
- A metal interconnect layer is formed on top of the FEOL layer during a back-end-of-line (BEOL) process, with interconnects to connect the FET to components on the substrate.
- A PDN is formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process.
- A through substrate resistive component is formed between the FEOL and B-BEOL layers, with connections to the FET and power supply rail through the PDN.
Potential Applications
- Semiconductor manufacturing
- Electronics industry
- ESD protection devices
Problems Solved
- Electrostatic discharge damage
- Improving ESD immunity
- Enhancing reliability of electronic devices
Benefits
- Increased protection against ESD events
- Improved reliability of electronic components
- Enhanced performance of semiconductor devices
Original Abstract Submitted
An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.
