18513211. MEMORY CONTROLLER AND DATA PROCESSING SYSTEM WITH MEMORY CONTROLLER simplified abstract (Huawei Technologies Co., Ltd.)

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MEMORY CONTROLLER AND DATA PROCESSING SYSTEM WITH MEMORY CONTROLLER

Organization Name

Huawei Technologies Co., Ltd.

Inventor(s)

Claudio Scordino of Pisa (IT)

MEMORY CONTROLLER AND DATA PROCESSING SYSTEM WITH MEMORY CONTROLLER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18513211 titled 'MEMORY CONTROLLER AND DATA PROCESSING SYSTEM WITH MEMORY CONTROLLER

Simplified Explanation

The memory controller described in the patent application is designed to manage access to a memory shared by multiple processing components in a data processing system. It allocates memory access bandwidth to each component based on their needs and adjusts this allocation based on timing information obtained from monitoring the duration of memory access operations.

  • Memory controller manages access to memory shared by multiple processing components
  • Allocates memory access bandwidth to each component based on their needs
  • Adjusts allocation based on timing information obtained from monitoring memory access operations

Potential Applications

This technology could be applied in:

  • High-performance computing systems
  • Data centers
  • Networking equipment

Problems Solved

  • Efficient memory access management in multi-component systems
  • Optimization of memory access bandwidth allocation
  • Improved system performance and resource utilization

Benefits

  • Enhanced system performance
  • Better resource utilization
  • Reduced bottlenecks in memory access

Potential Commercial Applications

Optimizing Memory Access Bandwidth Allocation for Improved System Performance


Original Abstract Submitted

A memory controller is provided and configured to control access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system. The memory controller comprises a control unit configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations. Moreover, the memory controller comprises a monitoring unit configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system. The control unit is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitoring unit.