18511133. MEMORY CELL WITH TOP ELECTRODE VIA simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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MEMORY CELL WITH TOP ELECTRODE VIA

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Ming-Che Ku of Hsinchu City (TW)

Harry-Hak-Lay Chuang of Zhubei City (TW)

Hung Cho Wang of Taipei (TW)

Tsun Chung Tu of Tainan City (TW)

Jiunyu Tsai of Hsinchu City (TW)

Sheng-Huang Huang of Hsinchu City (TW)

MEMORY CELL WITH TOP ELECTRODE VIA - A simplified explanation of the abstract

This abstract first appeared for US patent application 18511133 titled 'MEMORY CELL WITH TOP ELECTRODE VIA

Simplified Explanation

The present disclosure relates to an integrated chip with a memory device surrounded by a dielectric structure on a substrate. The memory device includes a data storage structure between a bottom electrode and a top electrode, each connected to interconnects via vias.

  • Memory device surrounded by dielectric structure
  • Data storage structure between bottom and top electrodes
  • Bottom electrode via connects to lower interconnect
  • Top electrode via connects to upper interconnect
  • Top electrode via has smaller width than bottom electrode via

Potential Applications

  • Semiconductor industry for memory devices
  • Electronics manufacturing for integrated chips

Problems Solved

  • Efficient data storage in a compact space
  • Improved connectivity between memory device and interconnects

Benefits

  • Higher memory capacity in a smaller footprint
  • Enhanced performance and reliability of integrated chips


Original Abstract Submitted

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.