18511102. ENLARGING CONTACT AREA AND PROCESS WINDOW FOR A CONTACT VIA simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
ENLARGING CONTACT AREA AND PROCESS WINDOW FOR A CONTACT VIA
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Li-Zhen Yu of New Taipei City (TW)
Cheng-Chi Chuang of New Taipei City (TW)
Chih-Hao Wang of Baoshan Township (TW)
Yu-Ming Lin of Hsinchu City (TW)
ENLARGING CONTACT AREA AND PROCESS WINDOW FOR A CONTACT VIA - A simplified explanation of the abstract
This abstract first appeared for US patent application 18511102 titled 'ENLARGING CONTACT AREA AND PROCESS WINDOW FOR A CONTACT VIA
Simplified Explanation
The integrated chip structure described in the patent application includes a substrate, gate electrode, spacer structure, conductive via, and liner.
- The substrate serves as the foundation for the chip structure.
- The gate electrode is positioned over the substrate to control the flow of electrical current.
- The spacer structure surrounds the gate electrode to provide support and insulation.
- The conductive via is placed on the gate electrode to facilitate electrical connections.
- The liner is arranged along the sidewalls of the spacer structure to enhance the structural integrity of the chip.
Potential Applications
This technology could be utilized in the manufacturing of advanced semiconductor devices, such as microprocessors and memory chips.
Problems Solved
This innovation addresses the need for improved integration and performance in chip structures, enhancing overall functionality and reliability.
Benefits
The integrated chip structure offers enhanced electrical connectivity, structural stability, and efficiency, leading to improved performance and durability in semiconductor devices.
Original Abstract Submitted
In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.
