18511064. WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Mao-Lin Huang of Hsinchu City (TW)

Chih-Hao Wang of Baoshan Township (TW)

Kuo-Cheng Chiang of Zhubei City (TW)

Jia-Ni Yu of New Taipei City (TW)

Lung-Kun Chu of New Taipei City (TW)

Chung-Wei Hsu of Hsinchu County (TW)

WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18511064 titled 'WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES

Simplified Explanation

The present disclosure describes an integrated chip with multiple transistor devices and gate electrode layers wrapping around the channel structures.

• The integrated chip includes multiple channel structures for transporting charge carriers within different transistor devices.
• Each transistor device has a corresponding gate electrode layer that wraps around the channel structure.
• The gate electrode layers continuously extend from around the channel structures to cover the adjacent gate electrode layers.

Potential Applications

This technology could be applied in:

• Semiconductor manufacturing
• Integrated circuit design
• Electronics industry

Problems Solved

This technology helps in:

• Improving transistor performance
• Enhancing chip integration
• Reducing power consumption

Benefits

The benefits of this technology include:

• Increased efficiency
• Higher transistor density
• Enhanced overall chip performance

Potential Commercial Applications

The potential commercial applications of this technology could be in:

• Mobile devices
• Computers
• Automotive electronics

Possible Prior Art

One possible prior art could be the use of multi-gate transistors in integrated circuits for improved performance and efficiency.

How does this technology compare to traditional integrated chip designs?

This article does not provide a direct comparison between this technology and traditional integrated chip designs.

What are the specific manufacturing processes involved in creating this integrated chip?

The article does not delve into the specific manufacturing processes involved in creating this integrated chip.

Original Abstract Submitted

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.