18510506. TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTOR

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Hung-Chang Sun of Kaohsiung City (TW)

Sheng-Chih Lai of Hsinchu County (TW)

Yu-Wei Jiang of Hsinchu (TW)

Kuo-Chang Chiang of Hsinchu City (TW)

TsuChing Yang of Taipei (TW)

Feng-Cheng Yang of Hsinchu County (TW)

Chung-Te Lin of Tainan City (TW)

TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 18510506 titled 'TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTOR

Simplified Explanation

The patent application describes a transistor with a unique structure involving an insulating layer, source and drain regions, a channel layer, a ferroelectric layer, and a gate electrode.

• The source and drain regions are located on opposite sidewalls of the insulating layer.
• The thickness of the source and drain regions, as well as the insulating layer, are approximately equal.
• The channel layer is positioned on top of the insulating layer, source, and drain regions.
• The ferroelectric layer is placed over the channel layer.
• The gate electrode is situated on the ferroelectric layer.

Potential Applications

• Advanced electronic devices
• Memory storage technology
• High-performance computing systems

Problems Solved

• Improved transistor performance
• Enhanced data retention capabilities
• Increased energy efficiency

Benefits

• Higher speed and efficiency in electronic devices
• Greater data storage capacity
• Reduced power consumption

Original Abstract Submitted

A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.