18508519. NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION
Organization Name
Inventor(s)
Cheheung Kim of Yongin-si (KR)
NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18508519 titled 'NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION
Simplified Explanation
The patent application describes a neuromorphic apparatus that processes multi-bit neuromorphic operations using a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller.
- The single axon circuit receives an i-th bit of an n-bit axon as its first input.
- The single synaptic circuit stores a j-th bit of an m-bit synaptic weight as its second input and outputs a synaptic operation value.
- The single neuron circuit calculates the result of the multi-bit neuromorphic operation between the axon and synaptic weight based on the synaptic operation value.
- The controller determines which bits are assigned to the axon and synaptic circuits during different time periods.
Potential Applications
- Neuromorphic computing - Artificial intelligence - Robotics - Brain-machine interfaces
Problems Solved
- Efficient processing of multi-bit neuromorphic operations - Mimicking biological neural networks - Real-time processing of complex data
Benefits
- Faster and more energy-efficient computation - Improved performance in pattern recognition tasks - Scalability for large-scale neural network implementations
Original Abstract Submitted
A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.
