18508367. GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS simplified abstract (International Business Machines Corporation)

GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS

Organization Name

International Business Machines Corporation

Inventor(s)

Alexander Reznicek of Troy NY (US)

Takashi Ando of Eastchester NY (US)

Jingyun Zhang of Albany NY (US)

Ruilong Xie of Niskayuna NY (US)

GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18508367 titled 'GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS

Simplified Explanation

The abstract describes a method for forming a semiconductor device with an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure present on a fin structure. The method involves removing the inner sidewall dielectric spacer, forming a channel epitaxial wrap around layer, removing the sacrificial gate structure, and forming a functional gate structure within the gate opening.

• Formation of inner and outer dielectric spacer combination structure on sacrificial gate structure
• Removal of inner sidewall dielectric spacer
• Formation of channel epitaxial wrap around layer on exposed fin structure
• Removal of sacrificial gate structure to create gate opening
• Formation of functional gate structure within gate opening

Potential Applications

The technology can be applied in the manufacturing of advanced semiconductor devices, particularly in the fabrication of high-performance transistors.

Problems Solved

This technology helps in improving the performance and efficiency of semiconductor devices by providing better control over the flow of current through the channel portion of the fin structure.

Benefits

- Enhanced device performance - Increased efficiency - Improved control over current flow

Potential Commercial Applications

The technology can be utilized in the production of various electronic devices such as smartphones, tablets, computers, and other consumer electronics.

Possible Prior Art

One possible prior art could be the use of dielectric spacers in semiconductor device fabrication to control the channel width and improve device performance.

Unanswered Questions

How does the inner and outer dielectric spacer combination structure impact the overall device performance?

The article does not delve into the specific effects of the inner and outer dielectric spacer combination structure on the device performance.

Are there any limitations or challenges associated with the formation of the channel epitaxial wrap around layer?

The article does not address any potential limitations or challenges that may arise during the formation of the channel epitaxial wrap around layer.

Original Abstract Submitted

A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.