18507138. GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Yu-Lien Huang of Jhubei City (TW)

Ching-Feng Fu of Taichung City (TW)

Huan-Just Lin of Hsinchu City (TW)

Fu-Sheng Li of Taichung (TW)

Tsai-Jung Ho of Changhua County (TW)

Bor Chiuan Hsieh of Taoyuan City (TW)

Guan-Xuan Chen of Taoyuan (TW)

Guan-Ren Wang of Hsinchu (TW)

GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18507138 titled 'GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE

Simplified Explanation

The method involves creating metal contacts in semiconductor devices.

• Form a mask layer on top of a first dielectric layer on a first source/drain and a second source/drain.
• Create an opening in the mask layer and the first dielectric layer to expose portions of the first source/drain and the second source/drain.
• Fill the opening with a metal layer covering the exposed portions of the first source/drain and the second source/drain.
• Form a gap in the metal layer to create a first metal contact and a second metal contact.
• The first metal contact electrically couples to the first source/drain, and the second metal contact electrically couples to the second source/drain.
• The gap separates the first metal contact from the second metal contact by less than nineteen nanometers.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit fabrication
• Nanotechnology research

Problems Solved

• Improving electrical connections in semiconductor devices
• Enhancing performance of electronic components
• Reducing resistance in metal contacts

Benefits

• Increased efficiency in semiconductor devices
• Enhanced conductivity in electronic circuits
• Improved overall performance of integrated circuits

Original Abstract Submitted

A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.