18506177. EMBEDDED FERROELECTRIC MEMORY CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
EMBEDDED FERROELECTRIC MEMORY CELL
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Tzu-Yu Chen of Kaohsiung City (TW)
Wen-Ting Chu of Kaohsiung City (TW)
Yong-Shiuan Tsair of Tainan City (TW)
EMBEDDED FERROELECTRIC MEMORY CELL - A simplified explanation of the abstract
This abstract first appeared for US patent application 18506177 titled 'EMBEDDED FERROELECTRIC MEMORY CELL
Simplified Explanation
The present disclosure describes an integrated chip structure with a first source/drain region, a second source/drain region, a select gate, a FeRAM device, and a transistor device on a substrate with a recessed surface.
- Integrated chip structure with multiple components on a substrate
- Select gate between first and second source/drain regions
- FeRAM device located over the substrate between select gate and first source/drain region
- Transistor device on upper surface of the substrate
- Recessed surface on the substrate below the upper surface, separated by a boundary isolation structure
- FeRAM device arranged over the recessed surface
Potential Applications
- Memory storage devices
- Integrated circuits
- Semiconductor devices
Problems Solved
- Efficient use of space on a substrate
- Integration of multiple components in a chip structure
- Improved performance of FeRAM devices
Benefits
- Higher density of components on a chip
- Enhanced functionality of FeRAM devices
- Improved overall performance of integrated circuits
Original Abstract Submitted
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.
