18501137. THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chao-I Wu of Zhubei City (TW)

Sai-Hooi Yeong of Zhubei City (TW)

Yu-Ming Lin of Hsinchu City (TW)

Han-Jong Chia of Hsinchu City (TW)

THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18501137 titled 'THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a three-dimensional memory device with first and second stacking structures and first and second conductive pillars.

• The first stacking structure consists of stacked first stacking layers along a vertical direction, each including a first gate layer, a first channel layer, and a first ferroelectric layer.
• The second stacking structure is laterally spaced from the first stacking structure and includes stacked second stacking layers along the vertical direction, each including a second gate layer, a second channel layer, and a second ferroelectric layer.
• The first and second gate layers are between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact with the first and second channel layers.

1. 1. 1. Potential Applications

• Non-volatile memory devices
• High-density data storage solutions
• Embedded memory in integrated circuits

1. 1. 1. Problems Solved

• Increasing memory density in a compact space
• Enhancing data retention and reliability
• Improving memory access speed

1. 1. 1. Benefits

• Higher memory capacity
• Faster data access
• Improved data security and reliability

Original Abstract Submitted

A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.