18498851. METHOD FOR FORMING INTERCONNECT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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METHOD FOR FORMING INTERCONNECT STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chun-Kai Chen of Kaohsiung (TW)

Jei Ming Chen of Tainan (TW)

Tze-Liang Lee of Hsinchu (TW)

METHOD FOR FORMING INTERCONNECT STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18498851 titled 'METHOD FOR FORMING INTERCONNECT STRUCTURE

Simplified Explanation

The method involves depositing layers over conductive features to create openings for exposing the top surface of the conductive feature.

  • First dielectric layer is deposited over a first conductive feature.
  • First mask layer is deposited over the first dielectric layer.
  • Second mask layer is deposited over the first mask layer.
  • A first opening is patterned in the first mask layer and the second mask layer.
  • A second opening is patterned in the bottom surface of the first opening, extending into the first dielectric layer.
  • The second opening has a smaller width than the first opening.
  • The first opening is extended into the first dielectric layer, and the second opening is extended through the first dielectric layer to expose the top surface of the first conductive feature.

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      1. Potential Applications
  • Semiconductor manufacturing
  • Microelectronics fabrication
  • Integrated circuit production
      1. Problems Solved
  • Precise patterning of openings in dielectric layers
  • Exposing specific areas of conductive features
      1. Benefits
  • Improved accuracy in creating openings
  • Enhanced control over the fabrication process
  • Higher quality and reliability of electronic components


Original Abstract Submitted

A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

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