18494784. PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Wei-Yu Chen of New Taipei City (TW)

An-Jhih Su of Taoyuan City (TW)

Chi-Hsi Wu of Hsinchu City (TW)

Der-Chyang Yeh of Hsin-Chu (TW)

Li-Hsien Huang of Hsinchu County (TW)

Po-Hao Tsai of Taoyuan City (TW)

Ming-Shih Yeh of Hsinchu County (TW)

Ta-Wei Liu of Hsinchu (TW)

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18494784 titled 'PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The package structure and manufacturing method involve a first package with semiconductor die, insulating encapsulation, and through insulator vias, a second package with semiconductor die and conductive pads, and solder joints connecting the two packages.

• Through insulator vias are encapsulated in the insulating encapsulation.
• Solder joints connect the first and second packages.
• Solder joints are larger than through insulator vias and equal to or larger than conductive pads in size.

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1. 1. 1. Potential Applications

• Semiconductor packaging
• Electronics manufacturing

1. 1. 1. Problems Solved

• Efficient electrical connection between semiconductor dies in different packages
• Improved reliability and performance of electronic devices

1. 1. 1. Benefits

• Enhanced electrical connectivity
• Increased reliability of electronic components
• Improved performance of electronic devices

Original Abstract Submitted

A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.