18494376. METHOD FOR FORMING VIA STRUCTURE WITH LOW RESISTIVITY simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
METHOD FOR FORMING VIA STRUCTURE WITH LOW RESISTIVITY
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Kuo-Chiang Tsai of Hsinchu City (TW)
Fu-Hsiang Su of Zhubei city (TW)
Ke-Jing Yu of Kaohsiung City (TW)
Chih-Hong Hwang of New Taipei City (TW)
Jyh-Huei Chen of Hsinchu City (TW)
METHOD FOR FORMING VIA STRUCTURE WITH LOW RESISTIVITY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18494376 titled 'METHOD FOR FORMING VIA STRUCTURE WITH LOW RESISTIVITY
Simplified Explanation
The method described in the patent application involves forming a semiconductor device structure by layering insulating materials, gate spacers, conductive gate stacks, insulating capping layers, and source/drain contact structures.
- Formation of first insulating layer and gate spacers
- Formation of first conductive gate stack and insulating material
- Covering gate stack and insulating material with insulating capping layers
- Formation of source/drain contact structure between gate spacer layers
- Ensuring top surface of first insulating layer is higher than insulating material and level with conductive gate stack
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- Potential Applications
- Semiconductor manufacturing
- Integrated circuit fabrication
- Electronic device production
- Problems Solved
- Improving semiconductor device performance
- Enhancing gate stack reliability
- Reducing leakage current
- Benefits
- Increased efficiency in semiconductor device production
- Enhanced performance of electronic devices
- Improved reliability of integrated circuits
Original Abstract Submitted
A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. The method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. The top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.
