18493051. MEMORY DEVICE AND OPERATION METHOD THEREOF simplified abstract (Samsung Electronics Co., Ltd.)

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MEMORY DEVICE AND OPERATION METHOD THEREOF

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

YOON-JOO Eom of Hwaseong-si (KR)

SEUNGJUN Bae of Hwaseong-si (KR)

HYE JUNG Kwon of Seoul (KR)

YOUNG-JU Kim of Hwaseong-si (KR)

MEMORY DEVICE AND OPERATION METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18493051 titled 'MEMORY DEVICE AND OPERATION METHOD THEREOF

Simplified Explanation

The memory device described in the patent application utilizes decision feedback equalization (DFE) technique to reduce bit errors caused by inter-symbol interference. Here are the key points of the innovation:

  • First data line driver circuit generates a first reference voltage set based on a first code and a second code associated with a first data line.
  • First data line driver circuit determines bit values of the first input data received through the first data line based on the first reference voltage set.
  • Second data line driver circuit similarly generates a second reference voltage set.
  • Reference voltages have levels based on DFE technique to reduce bit errors caused by inter-symbol interference.

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      1. Potential Applications
  • Memory devices in electronic devices such as smartphones, computers, and servers.
  • Communication systems where data integrity is crucial, such as in networking equipment.
      1. Problems Solved
  • Reducing bit errors caused by inter-symbol interference.
  • Improving data transmission reliability and accuracy.
      1. Benefits
  • Enhanced data integrity and reliability.
  • Improved performance of memory devices.
  • Reduction in data transmission errors.


Original Abstract Submitted

A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

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