18492504. 3D SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

3D SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Kohji Kanamori of SEONGNAM-SI (KR)

Jee Hoon Han of HWASEONG-SI (KR)

Seo-Goo Kang of SEOUL (KR)

Hyo Joon Ryu of HWASEONG-SI (KR)

3D SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18492504 titled '3D SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING SAME

Simplified Explanation

The semiconductor memory device described in the patent application includes:

• Lower stacked structure with lower metallic lines stacked on a substrate in a first direction
• Upper stacked structure with first and second upper metallic lines stacked on the lower structure
• Vertical structure penetrating both the upper and lower stacked structures, with a channel film and connection pad doped with N-type impurities
• First cutting line cutting the lower metallic lines and upper metallic lines
• Second cutting line spaced apart from the first cutting line in a different direction, cutting the metallic lines
• Sub-cutting lines cutting the upper metallic lines between the first and second cutting lines

Potential applications of this technology:

• Memory devices
• Integrated circuits
• Semiconductor devices

Problems solved by this technology:

• Efficient memory storage
• Improved performance of semiconductor devices
• Enhanced integration of components

Benefits of this technology:

• Higher memory capacity
• Faster data processing
• Increased reliability of semiconductor devices

Original Abstract Submitted

A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.