18486546. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Seunghwan Kim of Suwon-si (KR)

Yongkwan Lee of Suwon-si (KR)

Gyuhyeong Kim of Suwon-si (KR)

Jungjoo Kim of Suwon-si (KR)

Jongwan Kim of Suwon-si (KR)

Junwoo Park of Suwon-si (KR)

Taejun Jeon of Suwon-si (KR)

Junhyeung Jo of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18486546 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The semiconductor package described in the abstract includes a lower substrate with a lower interconnection layer, an upper substrate with a recessed surface and an upper interconnection layer, a semiconductor chip with connection pads, an interconnect structure, and an insulating member covering the chip and interconnect structure.

• Lower substrate with lower interconnection layer
• Upper substrate with recessed surface and upper interconnection layer
• Semiconductor chip with connection pads
• Interconnect structure connecting lower and upper interconnection layers
• Insulating member covering chip and interconnect structure

Potential Applications

The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics where compact and efficient semiconductor packaging is required.

Problems Solved

This technology solves the problem of efficiently connecting and insulating semiconductor chips within a package, allowing for improved performance and reliability of electronic devices.

Benefits

The benefits of this technology include improved electrical connections, reduced signal interference, enhanced thermal management, and overall increased reliability of electronic devices.

Potential Commercial Applications

The technology described in this patent application has potential commercial applications in the semiconductor industry, particularly in the manufacturing of advanced electronic devices where compact and reliable packaging is essential.

Possible Prior Art

One possible prior art for this technology could be the use of multi-layer ceramic substrates in semiconductor packaging to provide electrical connections and insulation for semiconductor chips. Another could be the use of through-hole vias in semiconductor packages for vertical interconnections between different layers.

=== What are the specific dimensions of the recessed surface on the upper substrate? The abstract does not provide specific dimensions for the recessed surface on the upper substrate.

=== How does the interconnect structure ensure reliable electrical connections between the lower and upper interconnection layers? The abstract does not detail the specific mechanism by which the interconnect structure ensures reliable electrical connections between the lower and upper interconnection layers.

Original Abstract Submitted

A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.