18485709. Structure and Method for Sealing a Silicon IC simplified abstract (Apple Inc.)
Contents
Structure and Method for Sealing a Silicon IC
Organization Name
Inventor(s)
Vidhya Ramachandran of Cupertino CA (US)
Sanjay Dabral of Cupertino CA (US)
SivaChandra Jangam of Milpitas CA (US)
Kunzhong Hu of Cupertino CA (US)
Structure and Method for Sealing a Silicon IC - A simplified explanation of the abstract
This abstract first appeared for US patent application 18485709 titled 'Structure and Method for Sealing a Silicon IC
Simplified Explanation
The abstract describes a chip sealing structure and method of manufacture. The chip structure includes a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from the back surface of the substrate to the top surface of the BEOL build-up structure. A conformal sealing layer covers at least a first chip edge sidewall and a portion of the top surface of the BEOL build-up structure, forming a lip around the top surface.
- The chip structure includes a substrate, a BEOL build-up structure, and chip edge sidewalls.
- A conformal sealing layer covers the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure.
- The sealing layer forms a lip around the top surface of the BEOL build-up structure.
Potential applications of this technology:
- Semiconductor manufacturing
- Integrated circuit packaging
Problems solved by this technology:
- Protecting the chip edge sidewalls and the top surface of the BEOL build-up structure from damage or contamination
- Enhancing the sealing and protection of the chip structure
Benefits of this technology:
- Improved reliability and durability of chip structures
- Enhanced performance of integrated circuits
- Increased protection against external factors such as moisture or dust.
Original Abstract Submitted
Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.
