18481931. SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM simplified abstract (Apple Inc.)
Contents
SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM
Organization Name
Inventor(s)
Sanjay Dabral of Cupertino CA (US)
Bahattin Kilic of Cupertino CA (US)
Jie-Hua Zhao of Cupertino CA (US)
Kunzhong Hu of Cupertino CA (US)
Suk-Kyu Ryu of Cupertino CA (US)
SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 18481931 titled 'SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM
Simplified Explanation
The abstract of the patent application describes multi-chip systems and structures for modular scaling. It mentions the use of an interfacing bar to couple adjacent chips, such as a communication bar for logic chips and a memory bar for memory chips coupled to a logic chip.
- Multi-chip systems and structures for modular scaling are described.
- An interfacing bar is utilized to couple adjacent chips.
- A communication bar may be used to couple logic chips.
- A memory bar may be used to couple multiple memory chips to a logic chip.
Potential applications of this technology:
- Modular scaling of multi-chip systems.
- Improved communication and data transfer between logic chips.
- Efficient coupling of multiple memory chips to a logic chip.
Problems solved by this technology:
- Simplifies the process of scaling multi-chip systems.
- Enhances communication and data transfer between chips.
- Facilitates efficient coupling of memory chips to a logic chip.
Benefits of this technology:
- Allows for flexible and scalable multi-chip systems.
- Improves overall performance and efficiency of the system.
- Enables efficient utilization of memory resources.
Original Abstract Submitted
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
