18480660. SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Dongho Kim of Hwaseong-si (KR)

Jihwang Kim of Cheonan-si (KR)

SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18480660 titled 'SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER

Simplified Explanation

The semiconductor package described in the patent application includes a semiconductor chip, a lower redistribution layer, a molding layer, and an upper redistribution layer.

• The lower redistribution layer is located under the semiconductor chip and includes a lower insulating layer at the central region and a portion of the edge region. The remaining portion of the edge region has a trench.
• There are multiple outer connecting terminals under the lower redistribution layer.
• The molding layer consists of a first molding section and a second molding section. The first molding section surrounds the side surface of the semiconductor chip, while the second molding section is in the trench and contacts the side surface of the lower insulating layer.
• An upper redistribution layer is provided on the molding layer.
• The side surface of the lower insulating layer and the side surface of the second molding section are coplanar with each other.

Potential applications of this technology:

• Semiconductor packaging for integrated circuits
• Electronic devices requiring compact and efficient packaging

Problems solved by this technology:

• Provides improved insulation and protection for the semiconductor chip
• Enables efficient redistribution of electrical connections
• Enhances the structural integrity of the semiconductor package

Benefits of this technology:

• Improved performance and reliability of semiconductor devices
• Compact and space-saving packaging solution
• Enhanced protection against external factors such as moisture and physical damage

Original Abstract Submitted

A semiconductor package including a semiconductor chip, a lower redistribution layer under the semiconductor chip, the lower redistribution layer including a lower insulating layer at a central region and at a portion of an edge region, and a trench at a remaining portion of the edge region, a plurality of outer connecting terminals under the lower redistribution layer, a molding layer including a first molding section and the second molding section, the first molding section being on the lower redistribution layer and surrounding a side surface of the semiconductor chip and the second molding section being in the trench and contacting a side surface of the lower insulating layer, and an upper redistribution layer on the molding layer may be provided. The side surface of the lower insulating layer and a side surface of the second molding section may be coplanar with each other.