18478373. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Munhyeon Kim of Hwaseong-si (KR)
Myung Gil Kang of Suwon-si (KR)
Wandon Kim of Seongnam-si (KR)
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18478373 titled 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The disclosed patent application describes a semiconductor device and a method of fabricating the same. Here is a simplified explanation of the abstract:
- The device consists of a substrate, an active pattern in the upper portion of the substrate, and a gate electrode that crosses the active pattern.
- The gate electrode extends in a direction that intersects with the direction of the active pattern.
- A first gate spacer covers a side surface of the gate electrode, and a first inhibition layer is present between the gate electrode and the first gate spacer.
- A gate insulating layer is located between the gate electrode and the active pattern.
- The gate insulating layer includes a high-k dielectric layer and a gate oxide layer.
- The gate oxide layer is positioned between the high-k dielectric layer and the active pattern.
- The high-k dielectric layer is situated between the gate oxide layer and the gate electrode.
Potential applications of this technology:
- This semiconductor device and fabrication method can be used in various electronic devices, such as integrated circuits, microprocessors, and memory devices.
- It can improve the performance and efficiency of these electronic devices by enhancing the gate insulating layer.
Problems solved by this technology:
- The disclosed device and method address the need for improved gate insulating layers in semiconductor devices.
- By incorporating a high-k dielectric layer and a gate oxide layer, the device can provide better insulation and reduce leakage current.
Benefits of this technology:
- The use of a high-k dielectric layer improves the gate insulating layer's capacitance, allowing for better control of the device's electrical properties.
- The gate oxide layer provides additional insulation, reducing leakage current and improving overall device performance.
- The fabrication method described in the patent application enables the production of semiconductor devices with enhanced gate insulating layers, leading to improved device performance and efficiency.
Original Abstract Submitted
Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.
