18478056. SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Kyoung Lim Suk of Suwon-si (KR)

Seokhyun Lee of Hwaseong-si (KR)

Jaegwon Jang of Hwaseong-si (KR)

SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18478056 titled 'SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE

Simplified Explanation

The disclosed patent application describes a semiconductor package that includes a redistribution substrate, at least one passive device, and a semiconductor chip. The passive device has a first terminal and a second terminal, and it is located within the redistribution substrate. The semiconductor chip is positioned on the top surface of the redistribution substrate and overlaps with at least a portion of the passive device.

  • The redistribution substrate consists of a dielectric layer that is in contact with the first lateral surface, the second lateral surface, and the bottom surface of the passive device.
  • There is a lower conductive pattern on the first terminal of the passive device.
  • A lower seed pattern is provided between the first terminal and the conductive pattern, and it is directly connected to the first terminal.
  • A first upper conductive pattern is present on the second terminal of the passive device.
  • A first upper seed pattern is provided between the second terminal and the first upper conductive pattern, and it is directly connected to the second terminal.

Potential applications of this technology:

  • This semiconductor package design can be used in various electronic devices that require compact and efficient packaging of semiconductor chips.
  • It can be applied in mobile devices, such as smartphones and tablets, to enhance their performance and reduce their size.
  • It can also be utilized in automotive electronics, medical devices, and other industries where miniaturization and high functionality are crucial.

Problems solved by this technology:

  • The disclosed semiconductor package design allows for vertical overlapping of the semiconductor chip and the passive device, which helps in reducing the overall footprint of the package.
  • It provides a more efficient and compact integration of the passive device and the semiconductor chip, leading to improved performance and reliability.
  • The design also enables better thermal management and electrical connectivity between the passive device and the semiconductor chip.

Benefits of this technology:

  • The compact size of the semiconductor package allows for more efficient use of space in electronic devices.
  • The improved integration and connectivity between the passive device and the semiconductor chip enhance the overall performance and reliability of the package.
  • The design enables better thermal management, reducing the risk of overheating and improving the longevity of the semiconductor chip.


Original Abstract Submitted

Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal

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