18475968. BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHOD simplified abstract (Samsung Electronics Co., Ltd.)
BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHOD
Organization Name
Inventor(s)
Gapkyoung Kim of Suwon-si (KR)
BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18475968 titled 'BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHOD
Simplified Explanation
The abstract describes a memory device that includes a memory module and a Built-In Self-Test (BIST) logic circuit. The BIST logic circuit consists of a pattern generator, an error correction code (ECC) encoder, and a parity control circuit.
- The pattern generator generates main data, which includes a first portion.
- The ECC encoder generates parity data based on the main data.
- The parity control circuit generates mask data based on the parity data and the main data.
- The parity control circuit also generates substituted parity data based on the mask data and the parity data.
- The pattern of the substituted parity data matches the pattern of the first portion of the main data.
Potential applications of this technology:
- Memory testing: The BIST logic circuit can be used to test the memory module by generating patterns and checking for errors in the data and parity.
- Error correction: The ECC encoder and parity control circuit help in detecting and correcting errors in the memory data.
- Data integrity: The technology ensures that the pattern of the substituted parity data matches the pattern of the first portion of the main data, ensuring data integrity.
Problems solved by this technology:
- Memory testing efficiency: The BIST logic circuit simplifies the process of testing memory by generating patterns and checking for errors internally, reducing the need for external testing equipment.
- Error detection and correction: The ECC encoder and parity control circuit help in identifying and correcting errors in the memory data, improving data reliability.
- Data integrity assurance: The matching pattern of the substituted parity data ensures that the memory data remains intact and consistent.
Benefits of this technology:
- Improved memory testing: The BIST logic circuit allows for efficient and accurate testing of memory modules, reducing the time and resources required for testing.
- Enhanced data reliability: The error correction capabilities provided by the ECC encoder and parity control circuit improve the reliability of the memory data.
- Data integrity assurance: The matching pattern of the substituted parity data ensures that the memory data remains consistent and free from corruption.
Original Abstract Submitted
A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
