18467521. MULTI-BIT ACCUMULATOR AND IN-MEMORY COMPUTING PROCESSOR WITH SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MULTI-BIT ACCUMULATOR AND IN-MEMORY COMPUTING PROCESSOR WITH SAME
Organization Name
Inventor(s)
Sungmeen Myung of Suwon-si (KR)
Dong-Jin Chang of Suwon-si (KR)
MULTI-BIT ACCUMULATOR AND IN-MEMORY COMPUTING PROCESSOR WITH SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18467521 titled 'MULTI-BIT ACCUMULATOR AND IN-MEMORY COMPUTING PROCESSOR WITH SAME
Simplified Explanation
The patent application describes a multi-bit accumulator that utilizes 1-bit Wallace trees, tristate logic circuits, and a shift-adder to perform addition and accumulation operations efficiently.
- 1-bit Wallace trees are used to perform add operations on single-bit input data.
- Tristate logic circuits output the result of the add operation of the 1-bit Wallace trees based on an enable signal.
- A shift-adder performs an accumulation operation on the result of the add operation by shifting based on a clock signal.
Potential Applications
The technology described in the patent application could be applied in:
- Digital signal processing systems
- Arithmetic logic units in microprocessors
- High-speed computing applications
Problems Solved
The innovation addresses the following issues:
- Improving the speed and efficiency of addition operations in digital circuits
- Reducing power consumption in accumulator circuits
- Enhancing the performance of arithmetic units in computing systems
Benefits
The technology offers the following benefits:
- Faster addition and accumulation operations
- Lower power consumption compared to traditional accumulator designs
- Improved overall performance of digital systems
Original Abstract Submitted
A multi-bit accumulator includes 1-bit Wallace trees each configured to perform an add operation on single-bit input data, tristate logic circuits each configured to output a result of the add operation of the 1-bit Wallace trees according to an enable signal provided to the tristate logic circuits, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the 1-bit Wallace trees by a shift operation based on a clock signal.
