18462610. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Woohyeong Kim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18462610 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a redistribution substrate with multiple semiconductor chips positioned on it, connected through redistribution layers and molding layers.
- The semiconductor package includes a redistribution substrate with first and second regions, first and second semiconductor chips positioned on the first region, and third and fourth semiconductor chips positioned on the second region.
- Each semiconductor chip is electrically connected to the redistribution layers on the redistribution substrate.
- The conductive posts on the first region electrically connect the first redistribution layer to the second redistribution layer.
- The second molding layer is on the second region of the redistribution substrate and on the third and fourth semiconductor chips.
Potential Applications
This technology can be applied in the manufacturing of advanced semiconductor packages for various electronic devices such as smartphones, tablets, and computers.
Problems Solved
This technology solves the problem of efficiently connecting multiple semiconductor chips in a compact package while maintaining electrical connectivity and structural integrity.
Benefits
The benefits of this technology include improved performance, increased functionality, and enhanced reliability of semiconductor packages for electronic devices. Additionally, it allows for more compact and efficient designs.
Original Abstract Submitted
A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.
