18461661. MEMORY SYSTEM, CONTROL DEVICE, AND METHOD simplified abstract (Kioxia Corporation)
Contents
- 1 MEMORY SYSTEM, CONTROL DEVICE, AND METHOD
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY SYSTEM, CONTROL DEVICE, AND METHOD - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY SYSTEM, CONTROL DEVICE, AND METHOD
Organization Name
Inventor(s)
Goichi Ootomo of Kawasaki Kanagawa (JP)
MEMORY SYSTEM, CONTROL DEVICE, AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18461661 titled 'MEMORY SYSTEM, CONTROL DEVICE, AND METHOD
Simplified Explanation
The memory system described in the patent application includes a control device that combines data from multiple circuits and transfers it at a higher rate, and then divides received data and distributes it to the circuits at a lower rate.
- The memory system includes a semiconductor memory device and a control device.
- The control device has circuits that transfer data to connected devices and a circuit that combines and transfers data at a higher rate.
- The control device also has a circuit that divides received data and distributes it to the circuits at a lower rate.
Potential Applications
This technology could be applied in:
- High-speed data transfer systems
- Memory systems requiring efficient data distribution
Problems Solved
This technology solves:
- Slow data transfer rates in memory systems
- Inefficient data distribution among circuits
Benefits
The benefits of this technology include:
- Faster data transfer rates
- Improved efficiency in data distribution
Potential Commercial Applications
A potential commercial application for this technology could be in:
- High-performance computing systems
Possible Prior Art
One possible prior art for this technology could be:
- Memory systems with separate data transfer and distribution circuits
Unanswered Questions
How does the technology handle data errors during transfer?
The patent application does not specify how data errors are managed during the high-speed transfer and distribution process.
What is the power consumption of the memory system with this technology?
The patent application does not mention the power consumption implications of implementing this technology in a memory system.
Original Abstract Submitted
According to one embodiment, a memory system includes a semiconductor memory device and a control device. The memory system includes a first device and first channels. The first channels are each connected to one or more second devices. The control device is connected to the first device via a second channel. The control device includes first circuits and a second circuit. The first circuits each execute data transfer to the second device as an access destination. The second circuit is provided between the first circuits and the second channel. The second circuit combines data from the first circuits and transfers the combined data to the second channel at a transfer rate higher than that of pre-combining data. The second circuit divides data received via the second channel and distributes pieces of divided data to the first circuits at a transfer rate lower than that of pre-dividing data.
