18457453. INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS simplified abstract (Intel Corporation)
Contents
INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS
Organization Name
Inventor(s)
Nicholas A. Thomson of Hillsboro OR (US)
Kalyan C. Kolluru of Portland OR (US)
Adam Clay Faust of Portland OR (US)
Frank Patrick O'mahony of Portland OR (US)
INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18457453 titled 'INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS
Simplified Explanation
The patent application describes integrated circuit structures with backside vias and related methods and devices. Here is a simplified explanation of the abstract:
- The integrated circuit structure includes a device layer with active devices.
- A first metallization layer is placed over the device layer, which includes a conductive pathway in contact with at least one of the active devices.
- A second metallization layer is located under the device layer and includes a second conductive pathway.
- A conductive via is present in the device layer, connecting at least one active device with the second conductive pathway.
Potential applications of this technology:
- Integrated circuits with improved connectivity and performance.
- Enhanced functionality and miniaturization of electronic devices.
- Increased efficiency and reliability of electronic systems.
Problems solved by this technology:
- Overcomes limitations in traditional integrated circuit structures by providing backside vias for improved connectivity.
- Addresses challenges in achieving efficient and reliable conductive pathways in complex electronic systems.
Benefits of this technology:
- Enables better integration and connectivity between different layers of an integrated circuit.
- Enhances the performance and functionality of electronic devices.
- Improves the efficiency and reliability of electronic systems.
Original Abstract Submitted
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.
