18456261. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Seunghoon Yeon of Suwon-si (KR)
Seungryong Oh of Suwon-si (KR)
Huiyeong Jang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18456261 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor package described in the abstract includes a first semiconductor chip with through electrodes and bonding pads, a second semiconductor chip with wiring layers, redistribution pads, and bonding pads, conductive bumps connecting the two chips, an adhesive layer, and flow prevention structures in the adhesive layer.
- The semiconductor package consists of two stacked semiconductor chips connected by conductive bumps.
- The first chip has through electrodes and bonding pads, while the second chip has wiring layers, redistribution pads, and bonding pads.
- The conductive bumps connect the bonding pads of the two chips.
- An adhesive layer fills the space between the conductive bumps to secure the connection.
- Flow prevention structures are present in the adhesive layer to prevent any issues in the test pad region.
Potential Applications
The technology described in this patent application could be applied in various semiconductor devices, such as integrated circuits, microprocessors, and memory chips.
Problems Solved
This technology solves the problem of efficiently stacking and connecting multiple semiconductor chips in a package while ensuring reliable electrical connections between them.
Benefits
The benefits of this technology include improved performance, increased functionality, and reduced size of semiconductor packages, leading to enhanced overall device performance.
Potential Commercial Applications
The technology described in this patent application could be utilized in the manufacturing of advanced electronic devices, such as smartphones, tablets, laptops, and other consumer electronics.
Possible Prior Art
One possible prior art related to this technology could be the use of stacked semiconductor chips in multi-chip modules for electronic devices.
Unanswered Questions
How does the adhesive layer prevent flow issues in the test pad region?
The flow prevention structures in the adhesive layer help to control the flow of the adhesive material, ensuring that it does not interfere with the test pads on the second semiconductor chip.
What materials are typically used for the conductive bumps in semiconductor packages?
The materials commonly used for conductive bumps in semiconductor packages include solder, gold, and copper, among others. These materials are chosen based on factors such as conductivity, reliability, and cost.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.
