18455031. METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS simplified abstract (HUAWEI TECHNOLOGIES CO., LTD.)

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METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS

Organization Name

HUAWEI TECHNOLOGIES CO., LTD.

Inventor(s)

Jun Yu of Dongguan (CN)

Guoyu Wang of Chengdu (CN)

You Li of Chengdu (CN)

Yongyao Li of Shenzhen (CN)

METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18455031 titled 'METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS

Simplified Explanation

The present disclosure describes a method and apparatus for optimizing a flash memory chip. Here are the key points:

  • The method involves write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point.
  • The trigger point helps in identifying the electrical level state of a write data signal (DQ) corresponding to the DQS trigger point.
  • The method determines if a trigger condition for monitoring the NFI is met, which is related to the working environmental data of the NFI.
  • If the trigger condition is met, test data is written to the memory and a margin test is performed on the NFI to check if it passes the test.
  • If the NFI fails the margin test, interface retraining of the NFI is initiated without disconnecting the disk.

Potential applications of this technology:

  • Flash memory optimization in various electronic devices such as smartphones, tablets, and laptops.
  • Improving the performance and reliability of flash memory chips used in data storage systems and servers.
  • Enhancing the efficiency of flash memory in automotive applications, such as infotainment systems and advanced driver-assistance systems (ADAS).

Problems solved by this technology:

  • Ensures that the NFI bus channels are optimized without the need for disk disconnection.
  • Helps in identifying and addressing issues related to the working environmental data of the NFI.
  • Enables efficient testing and optimization of flash memory chips without compromising their performance or reliability.

Benefits of this technology:

  • Improved performance and reliability of flash memory chips.
  • Enhanced data storage capabilities and faster data transfer rates.
  • Cost-effective optimization of flash memory without the need for extensive hardware modifications.
  • Reduced downtime and maintenance efforts by avoiding disk disconnection during optimization processes.


Original Abstract Submitted

Embodiments of the present disclosure provide a method for optimizing a flash memory chip and a related apparatus. The method comprises, after completing write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point that triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the trigger condition is related to working environmental data of the NFI; upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes a margin test; and upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI. In this way, the NFI bus channels can be optimized without disk disconnection.

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