18453108. Mitigating Row Hammer Attacks Through Memory Address Encryption simplified abstract (Apple Inc.)

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Mitigating Row Hammer Attacks Through Memory Address Encryption

Organization Name

Apple Inc.

Inventor(s)

Jeff Gonion of Campbell CA (US)

Mitigating Row Hammer Attacks Through Memory Address Encryption - A simplified explanation of the abstract

This abstract first appeared for US patent application 18453108 titled 'Mitigating Row Hammer Attacks Through Memory Address Encryption

Simplified Explanation

The system described in the patent application employs encryption on memory addresses generated by a source circuit for memory transactions, such as a CPU, GPU, embedded processors, microcontrollers, or peripheral devices. The encrypted memory address corresponds to the activated row for the memory transaction, instead of the original memory address generated by the source circuit.

  • Memory addresses generated by a source circuit are encrypted for security purposes.
  • The encrypted memory address corresponds to the row activated for the memory transaction.
  • This system can be used in various processors and peripheral devices for enhanced security.

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      1. Potential Applications
  • Data security in processors and peripheral devices.
  • Protection against memory address manipulation attacks.
      1. Problems Solved
  • Prevents unauthorized access to memory addresses.
  • Enhances security in memory transactions.
      1. Benefits
  • Improved data security.
  • Protection against memory-related cyber attacks.
  • Enhanced confidentiality in memory transactions.


Original Abstract Submitted

In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.