18452858. SEMICONDUCTOR DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR DEVICE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Pilkwang Kim of SUWON-SI (KR)

Seunghyun Song of HWASEONG-SI (KR)

Yoonsuk Kim of SUWON-SI (KR)

Gwangjun Kim of SUWON-SI (KR)

Jaemin Kim of SUWON-SI (KR)

SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18452858 titled 'SEMICONDUCTOR DEVICE

Simplified Explanation

The semiconductor device described in the patent application includes a gate structure with a gate dielectric layer and a gate electrode, as well as source/drain regions and multiple channel layers.

  • The gate structure has upper and lower portions, with the lower portion having inclined side surfaces sloped at acute angles.
  • The gate dielectric layer is positioned between the gate electrode and the channel layers, as well as between the gate electrode and the source/drain regions.

Potential Applications

  • High-performance transistors
  • Advanced electronic devices
  • Power management systems

Problems Solved

  • Improved control over the flow of electrical current
  • Enhanced efficiency and reliability of semiconductor devices
  • Increased speed and performance of electronic components

Benefits

  • Higher functionality and performance
  • Greater energy efficiency
  • Enhanced overall device reliability


Original Abstract Submitted

A semiconductor device includes an active region, a plurality of channel layers spaced apart from each other on the active region, a gate structure including a gate dielectric layer and a gate electrode, and source/drain regions on both sides of the gate structure. The gate structure includes an upper portion and lower portions. A first lower portion of the lower portions has a first lower surface, a first upper surface, and first and second side surfaces. Each of the first and second side surfaces includes a first inclined portion sloped at a first acute angle from the first lower surface and a second inclined portion sloped at a second acute angle from the first upper surface. The gate dielectric layer includes portions disposed between the gate electrode and the plurality of channel layers and between the gate electrode and the source/drain regions.