18452423. DIGITAL LOW-DROPOUT VOLTAGE REGULATOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
DIGITAL LOW-DROPOUT VOLTAGE REGULATOR
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Jaw-Juinn Horng of Hsinchu (TW)
DIGITAL LOW-DROPOUT VOLTAGE REGULATOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18452423 titled 'DIGITAL LOW-DROPOUT VOLTAGE REGULATOR
Simplified Explanation
The integrated circuit device described in the patent application includes rows of functional cells, with at least one row containing digital low-dropout voltage regulator (DLVR) cells. Each DLVR cell consists of transistors arranged in a cascode configuration, connected between various terminals within the cell height.
- DLVR cells in the integrated circuit device have an input terminal, an output terminal, a voltage supply terminal, and a reference voltage terminal.
- Transistors within the DLVR cells are arranged in pairs in a cascode configuration.
- The gate of one transistor in the pair is connected to the input terminal, while the gate of the other transistor is connected to the reference voltage terminal.
- Each terminal is made up of a metal track in the bottom metal layer and is located within the cell height.
Potential Applications
- Power management systems - Integrated circuits for electronic devices
Problems Solved
- Voltage regulation in integrated circuits - Efficient power management
Benefits
- Improved performance of electronic devices - Enhanced power efficiency - Compact design for integrated circuits
Original Abstract Submitted
In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.
