18448008. CMOS SCHMITT TRIGGER RECEIVER FOR THIN OXIDE TECHNOLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
CMOS SCHMITT TRIGGER RECEIVER FOR THIN OXIDE TECHNOLOGY
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Yung-Shun Chen of Taoyuan City (TW)
Chih-Chiang Chang of Taipei City (TW)
Yung-Chow Peng of Hsinchu (TW)
CMOS SCHMITT TRIGGER RECEIVER FOR THIN OXIDE TECHNOLOGY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18448008 titled 'CMOS SCHMITT TRIGGER RECEIVER FOR THIN OXIDE TECHNOLOGY
Simplified Explanation
The patent application describes a device with an inverter circuit, hysteresis control circuit, and high-side input level shifter for signal processing.
- The inverter circuit consists of PMOS and NMOS transistors connected in series to invert input signals.
- The hysteresis control circuit provides feedback to the transistors for stability and control.
- The high-side input level shifter shifts low input signal levels to higher levels for gate control of the PMOS transistors.
Potential Applications
- Signal processing in electronic devices
- Power management systems
- Motor control circuits
Problems Solved
- Signal inversion and level shifting
- Control and stability in transistor circuits
- Efficient power management
Benefits
- Improved signal processing capabilities
- Enhanced control and stability in circuits
- Increased efficiency in power management systems
Original Abstract Submitted
A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.
