18447826. ONE-TIME PROGRAMMABLE MEMORY BIT CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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ONE-TIME PROGRAMMABLE MEMORY BIT CELL

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Meng-Sheng Chang of Chu-bei City (TW)

Yao-Jen Yang of Hsinchu County (TW)

Min-Shin Wu of Taipei City (TW)

ONE-TIME PROGRAMMABLE MEMORY BIT CELL - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447826 titled 'ONE-TIME PROGRAMMABLE MEMORY BIT CELL

Simplified Explanation

The abstract describes a memory bit cell with antifuse transistors and selection transistors that can be programmed and read using word line signals.

  • Memory bit cell includes first and second memory cells with antifuse transistors and selection transistors
  • Antifuse transistors can be programmed to first or second state in response to word line program signal
  • Selection transistors provide access to antifuse transistors in response to word line read signal
  • First word line provides word line program signal, second word line provides word line read signal
  • Bit line is included in the memory bit cell

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      1. Potential Applications
  • Non-volatile memory applications
  • Embedded memory in integrated circuits
  • Memory storage in electronic devices
      1. Problems Solved
  • Providing a memory bit cell with antifuse transistors for programming and reading data
  • Enabling selective access to memory cells using word line signals
  • Improving memory storage efficiency and reliability
      1. Benefits
  • Faster programming and reading of memory cells
  • Higher data retention and reliability
  • Reduced power consumption compared to traditional memory technologies


Original Abstract Submitted

A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.

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