18447221. Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter simplified abstract (APPLE INC.)
Contents
- 1 Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
Organization Name
Inventor(s)
Reetika K. Agarwal of San Jose CA (US)
Abbas Komijani of Mountain View CA (US)
Hongrui Wang of San Jose CA (US)
Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447221 titled 'Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
Simplified Explanation
An electronic device is described that includes wireless circuitry with mixer circuitry. The mixer circuitry receives oscillator signals from a partial-fractional phase-locked loop (PLL). The PLL includes a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. The frequency divider receives a bitstream from a first order sigma delta modulator and a finite impulse response filter to implement the partial-fractional capability of the PLL. The first order sigma delta modulator outputs a periodic non-randomized output, and the finite impulse response filter increases the frequency of toggling of the output. This configuration reduces phase noise in the PLL.
- Wireless device with mixer circuitry receives oscillator signals from a partial-fractional PLL.
- Partial-fractional PLL includes a phase frequency detector, charge pump, loop filter, and frequency divider.
- Frequency divider receives a bitstream from a first order sigma delta modulator and a finite impulse response filter.
- First order sigma delta modulator outputs a periodic non-randomized output.
- Finite impulse response filter increases the frequency of toggling of the output.
- Configuration reduces phase noise in the PLL.
Potential Applications
- Wireless communication devices
- Radio frequency (RF) systems
- Mobile devices
- Internet of Things (IoT) devices
Problems Solved
- Reduces phase noise in the PLL
- Improves the performance of wireless communication devices
- Enhances the quality of RF systems
Benefits
- Improved signal quality
- Enhanced wireless communication performance
- Reduced interference and noise in RF systems
Original Abstract Submitted
An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
