18397906. NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION simplified abstract (Intel Corporation)
Contents
- 1 NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology compare to existing electronic packaging methods?
- 1.11 What materials are used in the base substrate and how do they affect the performance of the electronic package?
- 1.12 Original Abstract Submitted
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
Organization Name
Inventor(s)
Ravindranath Mahajan of Chandler AZ (US)
Debendra Mallik of Chandler AZ (US)
Sujit Sharan of Chandler AZ (US)
Digvijay Raorane of Chandler AZ (US)
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18397906 titled 'NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
Simplified Explanation
The abstract of the patent application describes electronic packages and methods of forming them, including a base substrate with through substrate vias, a die over the base substrate, a cavity within the base substrate, and a component in the cavity.
- Base substrate with through substrate vias
- Die placed over the base substrate
- Cavity within the base substrate, partially within the die's footprint
- Component located in the cavity
Potential Applications
The technology described in this patent application could be applied in the manufacturing of electronic devices, such as smartphones, tablets, and computers.
Problems Solved
This technology solves the problem of efficiently integrating components within electronic packages, allowing for compact and high-performance devices.
Benefits
The benefits of this technology include improved performance, reduced size and weight of electronic devices, and potentially lower manufacturing costs.
Potential Commercial Applications
The potential commercial applications of this technology could be in the consumer electronics industry, as well as in industries requiring compact and high-performance electronic components.
Possible Prior Art
One possible prior art could be the use of cavities in electronic packages to house components, but the specific configuration described in this patent application may be novel.
Unanswered Questions
How does this technology compare to existing electronic packaging methods?
This article does not provide a direct comparison to existing electronic packaging methods, leaving the reader to wonder about the specific advantages and disadvantages of this new approach.
What materials are used in the base substrate and how do they affect the performance of the electronic package?
The article does not delve into the materials used in the base substrate or their impact on the overall performance of the electronic package, leaving a gap in understanding for the reader.
Original Abstract Submitted
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
