18394854. SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS simplified abstract (Intel Corporation)
Contents
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
Organization Name
Inventor(s)
Sparsa Roychowdhury of West Bengal (IN)
Geethabai Biradar of Karnataka (IN)
Theo Drane of El Dorado Hills CA (US)
Achutha Kiran Kumar M V of Bangalore (IN)
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18394854 titled 'SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
Simplified Explanation
The techniques described in this patent application focus on automatically creating a software model for formal verification of semiconductor designs, enabling verification engineers to identify and fix bugs in both software and RTL designs efficiently.
- Simplified Explanation:
Techniques for creating a software model for formal verification of semiconductor designs are disclosed in this patent application, allowing verification engineers to detect and correct bugs in software and RTL designs effectively.
- Potential Applications:
- Formal verification of semiconductor designs - Bug detection and correction in software and RTL designs
- Problems Solved:
- Efficient bug detection and correction in software and RTL designs - Expansion of formal verification scope to cover both software and semiconductor designs
- Benefits:
- Saves significant design time - Reduces time to market for new products
- Potential Commercial Applications:
Optimizing Formal Verification Techniques for Semiconductor Designs
- Possible Prior Art:
One possible prior art could be the use of formal verification tools for software or semiconductor designs, but the specific techniques for automatically creating a software model as described in this patent application may be novel.
Questions:
1. How do these techniques improve the efficiency of bug detection and correction in software and RTL designs? 2. What specific benefits can be expected from implementing the software model created using the techniques described in this patent application?
Original Abstract Submitted
Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.
