18392740. AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES simplified abstract (Texas Instruments Incorporated)
Contents
- 1 AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
Organization Name
Texas Instruments Incorporated
Inventor(s)
Devanathan Varadarajan of Allen TX (US)
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18392740 titled 'AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
Simplified Explanation
The patent application abstract describes a method to test the functional memory interface logic of a core under test using a built-in-self-test (BIST) controller and a clock-gating circuit.
- The BIST controller generates test sequences for the core under test.
- The clock-gating circuit selectively supplies the test sequences to a memory input or memory output on the core under test.
- An initial data initialization is performed in BIST mode, followed by an at-speed functional mode to capture a desired memory output.
Potential Applications
The technology described in the patent application could be applied in the semiconductor industry for testing the functional memory interface logic of cores in integrated circuits.
Problems Solved
This technology helps in efficiently testing the memory interface logic of cores, ensuring their proper functionality and performance.
Benefits
The method provides a systematic approach to testing the memory interface logic of cores, improving the reliability and quality of integrated circuits.
Potential Commercial Applications
- Semiconductor manufacturing companies could utilize this technology to enhance the testing process of integrated circuits, leading to higher quality products.
- Companies specializing in core design and development could benefit from incorporating this method into their testing procedures to ensure the functionality of their cores.
Possible Prior Art
One possible prior art could be the use of BIST controllers and clock-gating circuits in testing other components of integrated circuits, such as processors or input/output interfaces.
Unanswered Questions
How does this method compare to traditional memory testing techniques?
This article does not provide a direct comparison between this method and traditional memory testing techniques.
What are the potential limitations or challenges of implementing this technology in real-world applications?
The article does not address any potential limitations or challenges that may arise when implementing this technology in real-world applications.
Original Abstract Submitted
Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.
