18392368. EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING simplified abstract (Intel Corporation)
Contents
- 1 EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING
Organization Name
Inventor(s)
Robert L. Sankman of Phoenix AZ (US)
Rahul N. Manepalli of Chandler AZ (US)
Robert Alan May of Chandler AZ (US)
Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US)
Bharat P. Penmecha of Phoenix AZ (US)
EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18392368 titled 'EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING
Simplified Explanation
The patent application describes semiconductor packages and methods for forming them. Here is a simplified explanation of the abstract:
- A semiconductor package includes a substrate and a core.
- An insulator material covers the core, with a portion between the core and the substrate.
- A via extends through the core from one surface to the other.
- A bridge die is in a recess in the substrate and connected to the via.
- An electronic component is attached to the via on the substrate surface.
Potential Applications
This technology could be used in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics.
Problems Solved
This innovation helps in creating more compact and efficient semiconductor packages, improving overall device performance and reliability.
Benefits
The benefits of this technology include increased functionality, reduced size, improved thermal management, and enhanced electrical performance of electronic devices.
Potential Commercial Applications
The potential commercial applications of this technology include semiconductor manufacturing companies, electronics manufacturers, and suppliers of components for electronic devices.
Possible Prior Art
One possible prior art could be the use of traditional wire bonding techniques in semiconductor packaging, which may not offer the same level of compactness and efficiency as the described method.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of cost-effectiveness?
The article does not provide information on the cost implications of implementing this technology compared to traditional packaging methods.
What are the environmental impacts of using this new semiconductor packaging technique?
The environmental sustainability aspects of this technology are not addressed in the article.
Original Abstract Submitted
Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.
