18374792. FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Seungmin Baek of Suwon-si (KR)
FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18374792 titled 'FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a chip-via composite substrate with a semiconductor chip, through vias, and redistribution wiring layers. The semiconductor chip is located in one region of the substrate, while the through vias are in another region, penetrating the substrate. The first redistribution wiring layer on the first surface of the substrate is connected to the chip pads and through vias, while the second redistribution wiring layer on the second surface is also connected to the through vias.
- Chip-via composite substrate with semiconductor chip, through vias, and redistribution wiring layers
- Semiconductor chip located in one region of the substrate
- Through vias in another region, penetrating the substrate
- First redistribution wiring layer on the first surface connected to chip pads and through vias
- Second redistribution wiring layer on the second surface connected to through vias
Potential Applications
The technology described in this patent application could be applied in various semiconductor packaging applications, such as in microprocessors, memory chips, and other integrated circuits.
Problems Solved
This technology solves the problem of efficiently connecting a semiconductor chip to external components through the use of through vias and redistribution wiring layers on a composite substrate.
Benefits
The benefits of this technology include improved electrical connectivity, reduced signal interference, and potentially smaller form factors for semiconductor packages.
Potential Commercial Applications
This technology could be commercially applied in the manufacturing of advanced semiconductor devices for consumer electronics, telecommunications equipment, and industrial applications.
Possible Prior Art
One possible prior art for this technology could be the use of through vias in semiconductor packaging to improve electrical connections and signal integrity.
Unanswered Questions
How does this technology compare to traditional semiconductor packaging methods?
This article does not provide a direct comparison between this technology and traditional semiconductor packaging methods.
What are the potential limitations or challenges in implementing this technology on a larger scale?
The article does not address any potential limitations or challenges in implementing this technology on a larger scale.
Original Abstract Submitted
A semiconductor package includes: a chip-via composite substrate including a substrate, a semiconductor chip, and a plurality of through vias, wherein the substrate has a first surface and a second surface opposite to the first surface and includes a first region and a second region around the first region, wherein the semiconductor chip is provided in the first region and has chip pads and circuit patterns that are electrically connected to the chip pads, and wherein the plurality of through vias is provided in the second region and penetrate the substrate; a first redistribution wiring layer provided on the first surface of the substrate and having first redistribution wirings that are electrically connected to the chip pads and the through vias; and a second redistribution wiring layer provided on the second surface of the substrate and having second redistribution wirings that are electrically connected to the through vias.
