18373017. ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
Organization Name
Inventor(s)
Byounggon Kang of Suwon-si (KR)
ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18373017 titled 'ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
Simplified Explanation
The abstract describes a clock gating cell that includes an inverter circuit, control circuits, and an output driver to generate an output clock signal.
- The clock gating cell includes an inverter circuit to generate an inverted clock signal.
- A first control circuit processes the inverted clock signal, an enable signal, and a scan enable signal to output a first internal signal.
- A second control circuit processes the first internal signal, the clock signal, the enable signal, and the scan enable signal to output a second internal signal.
- An output driver receives the second internal signal and outputs an output clock signal and a third internal signal.
Potential Applications
The clock gating cell technology can be applied in various digital systems and integrated circuits where power consumption needs to be optimized by controlling clock signals efficiently.
Problems Solved
The clock gating cell helps in reducing power consumption in digital systems by selectively enabling and disabling clock signals based on the system's operational requirements.
Benefits
- Improved power efficiency in digital systems - Enhanced control over clock signals for better performance optimization
Potential Commercial Applications
"Power-Efficient Clock Gating Cell Technology for Integrated Circuits"
Possible Prior Art
Prior art may include existing clock gating cell designs and power optimization techniques in digital systems.
Unanswered Questions
How does the clock gating cell technology impact overall system performance?
The article does not delve into the specific performance implications of implementing the clock gating cell technology.
Are there any limitations or drawbacks associated with using clock gating cells in digital systems?
The article does not address any potential limitations or drawbacks that may arise from the implementation of clock gating cells.
Original Abstract Submitted
A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.
