18372846. SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Jihwang Kim of Cheonan-si (KR)
SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18372846 titled 'SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device with a Package on Package (PoP) structure that reduces the total height of the package, enhances reliability, and implements a fine pitch between package substrates. The device includes a first package substrate with a body layer and a passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate with a body layer and a passivation layer, a first connection member outside the first semiconductor chip, and a gap filler between the first and second package substrates. The first package substrate has a first trench, the second package substrate has a second trench, and the first semiconductor chip is positioned between these trenches.
- The patent application describes a semiconductor device with a Package on Package (PoP) structure.
- The device reduces the total height of the package and enhances reliability.
- The device implements a fine pitch between package substrates.
- The device includes a first package substrate with a body layer and a passivation layer.
- The device includes a first semiconductor chip on the first package substrate.
- The device includes a second package substrate on the first package substrate with a body layer and a passivation layer.
- The device includes a first connection member outside the first semiconductor chip.
- The device includes a gap filler between the first and second package substrates.
- The first package substrate has a first trench.
- The second package substrate has a second trench.
- The first semiconductor chip is positioned between the first and second trenches.
Potential Applications
- This technology can be applied in the manufacturing of semiconductor devices.
- It can be used in various electronic devices such as smartphones, tablets, and computers.
Problems Solved
- The technology solves the problem of reducing the total height of semiconductor packages.
- It addresses the need for implementing a fine pitch between package substrates.
- The technology enhances the reliability of semiconductor devices.
Benefits
- The reduced height of the package allows for more compact and slim electronic devices.
- The fine pitch between package substrates enables better integration and connectivity.
- The enhanced reliability ensures improved performance and longevity of the semiconductor device.
Original Abstract Submitted
A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.
