18371152. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Hyeonseok Lee of Suwon-si (KR)
Hyeonjeong Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18371152 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a lower redistribution structure, an internal semiconductor chip on the upper surface of the lower redistribution structure, an upper redistribution structure connected to the lower redistribution structure through a conductive post, and a molding layer between the upper and lower redistribution structures. The upper redistribution structure contains an insulating layer with a redistribution pattern and a first material that transmits light, as well as a fiducial mark made of the first material.
- Lower redistribution structure
- Internal semiconductor chip
- Upper redistribution structure
- Conductive post
- Molding layer
- Insulating layer
- Fiducial mark
- Light-transmitting material
Potential Applications
The technology described in this patent application could be used in various semiconductor packaging applications, such as in microprocessors, memory chips, and other electronic devices that require precise alignment and electrical connections.
Problems Solved
This technology solves the problem of accurately aligning and connecting the internal semiconductor chip with the upper redistribution structure while providing a reliable and efficient packaging solution for semiconductor devices.
Benefits
The benefits of this technology include improved performance and reliability of semiconductor devices, enhanced light transmission capabilities for optoelectronic applications, and simplified manufacturing processes for semiconductor packaging.
Potential Commercial Applications
- Optoelectronic devices
- Microprocessors
- Memory chips
Possible Prior Art
One possible prior art for this technology could be semiconductor packaging methods that involve redistribution structures and fiducial marks for alignment purposes.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods?
This article does not provide a direct comparison with existing semiconductor packaging methods, leaving the reader to wonder about the specific advantages and disadvantages of this technology in relation to current practices.
What are the specific materials used in the fiducial mark and how do they contribute to the overall performance of the semiconductor package?
The article mentions a first material that transmits light and is used in the fiducial mark, but it does not elaborate on the specific properties or benefits of this material in the context of the semiconductor package.
Original Abstract Submitted
Provided is a semiconductor package including a lower redistribution structure, an internal semiconductor chip on an upper surface of the lower redistribution structure, an upper redistribution structure electrically connected to the lower redistribution structure through a conductive post, and a molding layer between the upper redistribution structure and the lower redistribution structure, the molding layer being adjacent to the internal semiconductor chip, wherein the upper redistribution structure includes an insulating layer including a redistribution pattern and a first material configured to transmit light, and a fiducial mark formed of the first material, and a lower surface of the fiducial mark is in contact with an upper surface of the molding layer.
