18367896. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does the concavo-convex pattern on the semiconductor devices improve thermal performance?
- 1.11 What are the specific materials used for the conductive bumps in this semiconductor package?
- 1.12 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
HWANYOUNG Choi of SUWON-SI (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18367896 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes an interposer mounted on a package substrate, with first and second semiconductor devices mounted on the interposer via conductive bumps and having concavo-convex patterns on their upper surfaces. A sealing member covers the semiconductor devices and exposes the concavo-convex patterns.
- The semiconductor package includes an interposer mounted on a package substrate.
- First and second semiconductor devices are mounted on the interposer via conductive bumps.
- The semiconductor devices have concavo-convex patterns on their upper surfaces.
- A sealing member covers the semiconductor devices and exposes the concavo-convex patterns.
Potential Applications
The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics that require compact and efficient semiconductor packaging.
Problems Solved
This technology solves the problem of efficiently mounting and protecting multiple semiconductor devices in a compact package, while also providing a reliable connection between the devices and the package substrate.
Benefits
The benefits of this technology include improved thermal performance, reduced footprint, enhanced reliability, and increased functionality in electronic devices that require advanced semiconductor packaging solutions.
Potential Commercial Applications
The potential commercial applications of this technology include the semiconductor packaging industry, electronics manufacturing companies, and semiconductor device manufacturers looking to enhance the performance and reliability of their products.
Possible Prior Art
One possible prior art in semiconductor packaging technology is the use of stacked die configurations with interposers to achieve compact and efficient packaging solutions. Another prior art could be the use of concavo-convex patterns on semiconductor devices for improved thermal management and electrical performance.
Unanswered Questions
How does the concavo-convex pattern on the semiconductor devices improve thermal performance?
The abstract mentions concavo-convex patterns on the semiconductor devices, but it does not elaborate on how these patterns specifically enhance thermal performance. Further details on the mechanism behind this improvement would be beneficial for a deeper understanding of the technology.
What are the specific materials used for the conductive bumps in this semiconductor package?
The abstract mentions conductive bumps used to mount the semiconductor devices on the interposer, but it does not specify the materials used for these bumps. Understanding the materials can provide insights into the electrical and mechanical properties of the semiconductor package.
Original Abstract Submitted
A semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps; first and second semiconductor devices on the interposer and spaced apart from each other, mounted on the interposer via second conductive bumps and having concavo-convex patterns respectively formed in upper surfaces thereof; and a sealing member on the interposer covering the first and second semiconductor devices and exposing the concavo-convex patterns. The concavo-convex pattern of the first semiconductor device includes a plurality of first pillar structures provided in the upper surface of a first region of the first semiconductor device and having a first width, and a plurality of second pillar structures provided in the upper surface of a second region of the first semiconductor device and having a second width greater than the first width.
