18367039. METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Myungsam Kang of Hwaseong-si (KR)
METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18367039 titled 'METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package and its associated methods. The package includes a substrate with two semiconductor chips and external terminals. The substrate has a core portion with first and second buildup portions on its top and bottom surfaces. These buildup portions consist of a dielectric pattern and a line pattern. The package also includes an interposer chip embedded in the core portion and electrically connected to the buildup portions. The interposer chip has a base layer, a redistribution layer on top of the base layer, and a via that penetrates the base layer and is exposed at its surface. The redistribution layer is connected to the line pattern of the first buildup portion, while the via is connected to the line pattern of the second buildup portion.
- The semiconductor package includes a substrate with two semiconductor chips and external terminals.
- The substrate has a core portion with first and second buildup portions on its top and bottom surfaces.
- The buildup portions consist of a dielectric pattern and a line pattern.
- An interposer chip is embedded in the core portion and electrically connected to the buildup portions.
- The interposer chip has a base layer, a redistribution layer, and a via.
- The redistribution layer is connected to the line pattern of the first buildup portion.
- The via penetrates the base layer and is connected to the line pattern of the second buildup portion.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- Integrated circuits and microprocessors used in various industries, including automotive, aerospace, and telecommunications.
Problems solved by this technology:
- Improved electrical connectivity between semiconductor chips and external terminals.
- Enhanced performance and reliability of semiconductor packages.
- Reduction in size and weight of electronic devices.
Benefits of this technology:
- Higher data transfer rates and faster processing speeds.
- Improved thermal management and heat dissipation.
- Increased integration density and miniaturization of electronic components.
- Enhanced overall performance and functionality of electronic devices.
Original Abstract Submitted
A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.
