18360378. Modified Manchester Encoding for Ultra-Low Power Interfaces simplified abstract (Apple Inc.)

Modified Manchester Encoding for Ultra-Low Power Interfaces

Organization Name

Apple Inc.

Inventor(s)

Shoichiro Sengoku of Dublin CA (US)

Modified Manchester Encoding for Ultra-Low Power Interfaces - A simplified explanation of the abstract

This abstract first appeared for US patent application 18360378 titled 'Modified Manchester Encoding for Ultra-Low Power Interfaces

Simplified Explanation

The present disclosure describes techniques for improving the generation of data signals with embedded clock information in an interface between a host processor device and a peripheral device, such as a camera or sensor. The goal is to make the data signals more rate-flexible and power efficient.

• The techniques involve embedding a clock signal into a data signal to minimize the number of channels needed.
• The system allows for a variable link rate without the need for a phase lock loop (PLL) or long link training times at the receiver, which can consume a lot of power and on-chip area.
• A modified Manchester encoding scheme is used, where a fixed delay is used for mid-bit transitions, independent of the link rate.
• This modified encoding scheme achieves the dual aims of rate flexibility and power efficiency for an improved data signal interface with embedded clock information.

Potential applications of this technology:

• This technology can be used in various communication systems where a host processor device needs to interface with a peripheral device, such as cameras, sensors, or other data-intensive devices.
• It can be applied in industries such as consumer electronics, automotive, medical devices, and industrial automation.

Problems solved by this technology:

• The technology solves the problem of generating data signals with embedded clock information that are rate-flexible and power efficient.
• It eliminates the need for a phase lock loop (PLL) and long link training times, which can consume significant power and on-chip area.

Benefits of this technology:

• The embedded clock information in the data signals allows for a more efficient and streamlined communication between the host processor device and the peripheral device.
• The rate flexibility of the data signals enables them to adapt to different link rates without the need for complex synchronization mechanisms.
• The power efficiency of the system reduces power consumption and can lead to longer battery life in portable devices.
• The simplified interface design reduces the complexity and cost of implementing the communication system.

Original Abstract Submitted

The present disclosure relates generally to an interface between a host processor device and a peripheral device, such as a camera or sensor, and, more particularly, to improving the generation of data signals with embedded clock information to be more rate-flexible and power efficient. Improved techniques are described herein to embed a clock signal into a data signal (e.g., to minimize the number of channels needed)—while allowing for a variable link rate and avoiding the need for a phase lock loop (PLL) and/or long link training times at the receiver, which can consume large amounts of power and on-chip area. In some embodiments, a modified Manchester encoding scheme, e.g., using a fixed delay for its mid-bit transitions (and wherein the delay is independent of link rate), is used to achieve the dual aims of rate flexibility and power efficiency for an improved data signal interface with embedded clock information.