18360056. SEMICONDUCTOR PACKAGES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGES
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18360056 titled 'SEMICONDUCTOR PACKAGES
Simplified Explanation
The semiconductor package described in the patent application comprises a first die, a second die on the first die, and connection terminals. The first die includes a first silicon substrate with first through vias, first chip pads, and a first dummy pattern on the upper side of the substrate. The second die includes a second silicon substrate with second through vias.
- The semiconductor package includes a first die with a first silicon substrate and a second die with a second silicon substrate.
- The first die has first through vias, first chip pads, and a first dummy pattern.
- The second die has second through vias.
- Connection terminals and first chip pads are in contact and electrically connected.
- The first dummy pattern includes a metal film or a polymer film.
- Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
- Problems Solved
- Improved electrical connection between dies
- Enhanced reliability of semiconductor packages
- Benefits
- Increased efficiency in semiconductor packaging
- Better performance and durability of electronic devices
Original Abstract Submitted
Provided is a semiconductor package. The semiconductor package may comprise a first die, a second die on the first die, and connection terminals, the first die comprises: a first silicon substrate that has a lower side and an upper side opposite to the lower side, first through vias, first chip pads, and a first dummy pattern on the upper side of the first silicon substrate, the first dummy pattern having a grid shape from a plan view and at least partially surrounding each of the first chip pads, the second die comprises: a second silicon substrate that has a lower side and an upper side opposite to the lower side, and second through vias, wherein the connection terminals and the first chip pads are in contact with each other and are electrically connected, respectively, and wherein the first dummy pattern includes a metal film or a polymer film.
