18355824. Architecture for Computing System Package simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
Architecture for Computing System Package
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Chieh-Yen Chen of Taipei City (TW)
Chuei-Tang Wang of Taichung City (TW)
Chung-Hao Tsai of Huatan Township (TW)
Architecture for Computing System Package - A simplified explanation of the abstract
This abstract first appeared for US patent application 18355824 titled 'Architecture for Computing System Package
Simplified Explanation
The method described in the patent application involves the formation of a reconstructed wafer. This process includes several steps:
1. Forming a redistribution structure over a carrier. 2. Bonding a first plurality of memory dies over the redistribution structure. 3. Bonding a plurality of bridge dies over the redistribution structure. 4. Bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. 5. Each of the bridge dies interconnects and is overlapped by corner regions of four of the logic dies. 6. Bonding a second plurality of memory dies over the plurality of logic dies. 7. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
Bullet points explaining the patent/innovation:
- The method involves the formation of a reconstructed wafer by bonding memory dies, bridge dies, and logic dies over a redistribution structure.
- The bridge dies interconnect and are overlapped by corner regions of the logic dies.
- The memory dies and logic dies are arranged in separate arrays on the reconstructed wafer.
Potential applications of this technology:
- Semiconductor manufacturing: The method can be used in the production of advanced semiconductor devices, such as memory modules and integrated circuits.
- Electronics industry: The reconstructed wafer can be utilized in various electronic devices, including smartphones, computers, and gaming consoles.
Problems solved by this technology:
- Space optimization: The overlapping of bridge dies by corner regions of logic dies allows for efficient use of space on the wafer, enabling higher component density.
- Improved interconnectivity: The interconnection between bridge dies and logic dies enhances the overall performance and functionality of the reconstructed wafer.
Benefits of this technology:
- Increased memory capacity: The bonding of multiple memory dies in separate arrays allows for higher memory capacity on the reconstructed wafer.
- Enhanced performance: The interconnectivity between bridge dies and logic dies improves data transfer and processing speed, resulting in improved performance of electronic devices.
Original Abstract Submitted
A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
